DC-DC converters are widely utilized for converting an input voltage to an output voltage at high efficiency. DC-DC converters are available in various topologies including buck converters, boost converters and buck-boost converters, as well as other topologies.
FIG. 1 shows an example buck converter generally as 100. The converter has a control logic circuit 102 which receives an input signal related to the output voltage (not shown) and generates a control signal GD_IN which is coupled to a gate driver circuit 104. The signal GD_IN may be a pulse width modulated (PWM) signal, for example. The gate driver 104 converts the signal GD_IN to a drive signal G_HSD for a high-side transistor 106 and G_LSD for a low-side transistor 108. The high-side transistor 106 and low-side transistor 108 are coupled in series between the input voltage and ground and have a switching node SW therebetween. The switching node is coupled to one terminal of inductor 114 the other terminal of which is coupled to the output voltage. An output capacitor 116 is coupled between the output voltage and ground. The circuit shown in FIG. 1 also shows an optional high-side current limit circuit 110 and low-side current limit circuit 112, which are known in the art.
The gate driver circuit 104 has as one of its functions and anti shoot-through function which prevents both the high-side transistor 106 and low-side transistor 108 from being on at the same time. If both transistors were to be on at the same time it would be a virtual short between the input voltage and ground which not only dramatically reduces the efficiency of the converter, it may produce irreversible damage to the transistors resulting in a failure of the DC-DC converter. Another function of the gate driver 104 is to generate a drive signal having sufficient strength to charge the gate capacitances of the high-side transistor 106 and low-side transistor 108.
A prior art digital gate drive circuit is shown in FIG. 2 generally as 200. The gate drive circuit 200 receives two input signals. The first signal GD_EN received at terminal 204 is an active low-enable signal which is used to tri-state the gate driver and place both the high-side and low-side transistors in an off condition. The second signal GD_IN is received terminal 202. When the signal is low, the high-side transistor 106 is ON and when the signal is high this transistor is OFF and the low-side transistor 108 is ON. The drive circuit for the high-side transistor and low-side transistor are identical and only the high-side circuit will be described. In this embodiment, the high-side transistor is PMOS transistor and the low-side transistor is in an NMOS transistor. Those skilled in the art recognize that, if the high-side transistor is an NMOS transistor instead of a PMOS transistor, a signal of opposite polarity is needed for driving the high-side transistor. This signal could be the signal on line 238, for example.
The high-side driver comprises a two input NOR gate 208 having one input coupled to signal GD_IN and another input coupled to the inverted signal GD_EN. The output of NOR gate 208 is coupled through inverter 210 to an input of a two input OR gate 212. The second input of OR gate 212 is coupled to the signal G_LSD via link 240, which is a drive signal for the low-side transistor 108. The output of OR gate 212 is connected to a string of inverters 214, 216, 218 and 220 the output of which generates the high-side drive signal G_HSD at terminal 222. Each of the inverters 214, 216, 218 and 220 generates a higher current signal than the circuit that precedes it, typically by three or four times the input current. Thus the number of inverters (or buffers) in the drive circuit is determined by the drive requirements of the high-side PMOS transistor 106. These two requirements dictate the propagation delay of the string of inverters as the number and size of capacitances to be charged increases.
The enable signal GD_EN is active low, so it will be high when the converter is operating. The signal GD_IN is low to turn the transistor 106 ON. These two signals are input to NOR gate 208, generating a digital zero at the output. This signal is inverted by inverter 210 and input to OR gate 212. The other input of OR gate 212 is the drive signal for the low-side transistor 106, which will be low if that transistor is OFF. The output of OR gate 212 is therefore low which results in a signal on terminal 222 that is also low, thus turning ON high-side PMOS transistor 106.
FIG. 3 illustrates the problem with driver circuit 200 if the input pulse GD_IN from control logic 102 to gate driver 104 is too narrow. In FIG. 3 an NMOS transistor was used as the high-side transistor and the gate drive signal would be the signal on line 238 shown in FIG. 2, for example. In FIG. 3, signal 302 represents the output current. Signal 304 represents the current through the high-side transistor 106 and signal 305 represents the current through the low-side transistor 108. Signal 310 represents the gate voltage signal having an input pulse 306 which has a leading edge 308. Signal 312 represents the voltage on the gate of the low-side transistor 106 and signal 314 represents the voltage on the gate of high-side transistor 108. Signal 324 represents the drain-to-source voltage the high-side transistor 106 and signal 326 represents the drain-to-source voltage of the low-side transistor 108. The plurality of inverters 214, 216, 218, 220 (buffers) generate a delay between the time the pulse is received on line 202 and a gate signal is provided to turn ON one of the output transistor 106, 108 and turn the transistor 106 OFF. Thus, the time between leading edge 308 of pulse 306 and time required to turn OFF transistor 108 is too short so that, as indicated at 316, the low-side transistor 108 is still ON while the high-side transistor 106 is turning ON and, as indicated at 318, the low-side transistor is turning ON before the high-side transistor has turned OFF. This, along with the parasitic inductance of the circuit, causes ringing, as shown at 320, 322, and 330, 332. This can cause shoot-through and the loss of stability of the converter as shown at 320, 322 and 330, 332.
Thus, there is a need for a gate driver circuit that can provide appropriate drive signals to the high-side and low-side transistors to avoid shoot-through and loss of control of the converter.